This invention relates to microelectronic devices and fabrication methods therefor, and more particularly to microelectronic packages and packaging methods.
In packaging microelectronic devices such as integrated circuits (also referred to as integrated circuit chips or simply as chips) on printed circuit boards or other integrated circuit mounting substrates, the integrated circuits generally are mounted parallel to and facing the printed circuit board such that a face of the integrated circuit is adjacent a face of the printed circuit board. This packaging technology can allow a large number of input/output connections to be provided between the integrated circuits and the printed circuit board, especially when solder bump technology is used, which can cover the entire face of the integrated circuits with solder bump connections. Unfortunately however, this packaging technology may limit the packaging density, because the large faces of the integrated circuit chips are mounted adjacent the face of the printed circuit board. Moreover, this packaging technology may limit the speed of the integrated circuits due to the relatively long interconnection lines on the printed circuit board.
In order to increase the packaging density of chips on the printed circuit board, three-dimensional packaging technologies also have been proposed, wherein the chips are mounted orthogonal to the circuit board so that a chip edge is adjacent the face of the circuit board. See for example U.S. Pat. No. 4,266,282 to Henle, et al. entitled Vertical Semiconductor Integrated Circuit Chip Packaging; U.S. Pat. No. 5,347,428 to Carson, et al. entitled Module Comprising IC Memory Stack Dedicated to and Structurally Combined with an IC Microprocessor Chip and U.S. Pat. No. 5,432,729 to Carson, et al. entitled Electronic Module Comprising a Stack of IC Chips Each Interacting with an IC Chip Secured to the Stack. In these patents, solder bump technology is used to connect the edges, rather than the faces, of integrated circuit chips to a substrate. Unfortunately, an edge-to-face connection may be difficult and/or costly to produce.
Moreover, in using solder bump technology to interconnect a three-dimensional package, it may be difficult to fabricate the solder bump to bridge from one substrate to another. In particular, it may be difficult to form solder that extends beyond the edge of a chip because the chip sawing or dicing operation may remove or damage the solder that extends beyond the chip edge. Moreover, during solder reflow, it is well known that the solder takes the shape of a hemisphere or partial hemisphere on a contact pad. Thus, it may be difficult to cause the solder on one contact pad to extend onto another contact pad, in a three-dimensional package. Even if solder is placed on pair of adjacent contact pads in a three-dimensional package, it may be difficult to cause the reflowed solder to join up, rather than forming individual solder bumps.
A major advance in three-dimensional microelectronic packaging that uses solder bump technology to interconnect a three-dimensional package is described in U.S. Pat. No. 5,793,116 to the present inventor Rinne, et al. entitled Microelectronic Packaging Using Arched Solder Columns, the disclosure of which is hereby incorporated herein by reference in its entirety. As described therein, a microelectronic package may be formed in which solder bumps on one substrate are expanded, to thereby extend to and contact a second substrate and thereby form a solder connection. In particular, a first microelectronic substrate is oriented relative to a second microelectronic substrate, such than an edge of the second microelectronic substrate is adjacent the first microelectronic substrate. One of the first and second microelectronic substrates includes a plurality of solder bumps thereon, adjacent the edge of the second microelectronic substrate. The plurality of solder bumps are expanded to extend to and contact the other of the first and second microelectronic substrates.
In the above-cited Rinne et al. ""116 patent, the plurality of solder bumps may be expanded by reflowing additional solder from an elongated, narrow solder-containing region adjacent the solder bump. into the solder bump. This region also may be referred to as a solder reservoir. Surface tension from the elongated solder-containing region can cause the solder to flow from the elongated solder-containing region into the solder bump, thereby expanding the volume of the solder bump and causing it to extend to and contact the other substrate. The plurality of solder bumps may be formed on the second microelectronic substrate adjacent the edge thereof. The solder bumps are caused to extend laterally beyond the edge of the second microelectronic substrate, to thereby contact the first microelectronic substrate. The solder bumps may be caused to extend laterally by reflowing additional solder into the plurality of solder bumps from the elongated, solder region adjacent the solder bump. Accordingly, solder bumps may be caused to bridge a gap to extend onto and contact an adjacent pad.
This breakthrough technology also is described in U.S. Pat. No. 5,892,179 to the present inventor Rinne, et al. entitled Solder Bumps and Structures for Integrated Redistribution Routing Conductors; U.S. Pat. No. 5,963,793 to the present inventor Rinne, et al. entitled Microelectronic Packaging Using Arched Solder Columns and U.S. Pat. No. 5,990,472 to the present inventor Rinne entitled Microelectronic Radiation Detectors for Detecting and Emitting Radiation Signals. The disclosures of all of these patents are hereby incorporated herein by reference in their entirety.
Microelectronic packages according to embodiments of the present invention include a first microelectronic substrate, a second microelectronic substrate that is oriented at an acute angle relative to the first microelectronic substrate, and a plurality of first solder bumps between the first and second microelectronic substrates, adjacent an edge of the second microelectronic substrate, that connect (electrically and/or mechanically) the second microelectronic substrate to the first microelectronic substrate and that are confined to within the edge of the second microelectronic substrate. The edge of the second microelectronic substrate is adjacent the vertex of the acute angle.
In other embodiments, a third microelectronic substrate also may be provided on the first microelectronic substrate that laterally overlaps the second microelectronic substrate. A plurality of second solder bumps connect the third microelectronic substrate to the first microelectronic substrate. In some embodiments, the second and third microelectronic substrates are oriented parallel to one another at the acute angle relative to the first microelectronic substrate. In other embodiments, the plurality of second solder bumps are adjacent a first edge of the third microelectronic substrate and opposite a second edge of the third microelectronic substrate, wherein the second edge of the third microelectronic substrate is adjacent the vertex and wherein the first edge of the third microelectronic substrate is opposite the vertex.
Embodiments of the present invention stem from a realization that if integrated circuits are mounted on a printed circuit board at an acute angle rather than perpendicular thereto, the acute angle may be limited so that the solder bumps can bridge from the integrated circuit to the printed circuit board without the need to expand the solder bumps during reflow. Accordingly, solder reservoirs. which can be difficult and/or costly to produce, need not be used for three-dimensional packaging. Moreover, by allowing multiple integrated circuit dies to laterally overlap on the printed circuit board, an increase in packaging density and/or reduced signal path lengths can be obtained compared to conventional mounting of integrated circuits on printed circuit boards. In particular, integrated circuit chips may be nested within one another so as to allow a small form factor.
Embodiments of microelectronic packages according to the invention can include a first microelectronic substrate and a second microelectronic substrate that is oriented at an acute angle relative to the first microelectronic substrate. The acute angle includes a vertex. A plurality of first solder bumps extend between the first and second microelectronic substrates, adjacent an edge of the second microelectronic substrate at the vertex of the acute angle, to connect the second microelectronic substrate to the first microelectronic substrate. The plurality of solder bumps are confined to within the edge of the second microelectronic substrate. A third microelectronic substrate also is oriented at the acute angle relative to the first microelectronic substrate, parallel to and laterally overlapping the second microelectronic substrate. A plurality of second solder bumps also extend between the first and third microelectronic substrates. adjacent an edge of the second microelectronic substrate at the vertex of the acute angle. The plurality of second solder bumps electrically and mechanically connect the third microelectronic substrate to the first microelectronic substrate and are confined to within the edge of the third microelectronic substrate. The second and third microelectronic substrates preferably are free of solder reservoir connections to the respective plurality of first and second solder bumps. Stated differently, sub-hemispherical, rather than super-hemispherical, solder bumps may be formed.
According to other embodiments, a plurality of integrated circuits are located on an integrated circuit mounting substrate, such as a printed circuit board. The plurality of integrated circuits are oriented parallel to each other and at an acute angle relative to the integrated circuit mounting substrate. Each of the integrated circuits includes first and second opposing faces and first and second opposing edges, wherein the first faces and the first edges are adjacent the integrated circuit mounting substrate and the second faces and second edges are opposite the integrated circuit mounting substrate. A plurality of solder bumps on the first faces adjacent the first edges of the integrated circuits extend between the integrated circuits and the integrated circuit substrate, and also extend to adjacent the first face of an adjacent integrated circuit. The respective first faces of the integrated circuits may rest upon the respective second faces of a respective adjacent integrated circuit. In other embodiments, the integrated circuits are identical integrated circuits, and in other embodiments the identical integrated circuits are flash memory integrated circuits. The acute angles may be as described above, and the integrated circuits and the integrated circuit mounting substrate may be free of solder reservoir connections.
In other embodiments of microelectronic packages according to the present invention, a second microelectronic substrate is oriented at an acute angle relative to the first microelectronic substrate. The acute angle includes a vertex. A plurality of first solder bumps extend between the first and second microelectronic substrates, adjacent a first edge of the second microelectronic substrate that is adjacent the vertex, to connect the second microelectronic substrate to the first microelectronic substrate. A third microelectronic substrate is provided on the first microelectronic substrate that extends between the second microelectronic substrate and the first microelectronic substrate. A plurality of second solder bumps are located adjacent a first edge of the third microelectronic substrate, and opposite a second edge of the third microelectronic substrate. The second solder bumps connect the third microelectronic substrate to the first microelectronic substrate, such that the second edge of the third microelectronic substrate is adjacent the vertex and the first edge of the third microelectronic substrate is opposite the vertex. In first embodiments, the plurality of first and second solder bumps are confined to within the respective first and second edges of the respective second and third microelectronic substrates. In other embodiments they need not be so confined.
Other embodiments of microelectronic packages according to the present invention include a first microelectronic substrate and a second microelectronic substrate having first and second opposing edges and canted on the first microelectronic substrate such that the first edge is spaced further away from the first microelectronic substrate than the second edge. A third microelectronic substrate is provided on the second microelectronic substrate, opposite the first microelectronic substrate and extending in a first direction onto the second microelectronic substrate towards the first edge and in a second direction that is opposite the first direction away from and beyond the second microelectronic substrate. A plurality of first solder bumps may be provided adjacent the first edge that electrically and mechanically connect the second microelectronic substrate to the first microelectronic substrate. A plurality of second solder bumps also may be provided in non-overlapping relationship with the second microelectronic substrate that electrically and mechanically connect the third microelectronic substrate to the first microelectronic substrate. The second microelectronic substrate preferably is free of solder bumps adjacent the second edge and the third microelectronic substrate preferably is free of solder bumps that overlap the second microelectronic substrate. In other embodiments, the second and third microelectronic substrates are identical integrated circuit chips. In other embodiments they are identical integrated circuit memory chips such as flash memory chips.
Other embodiments of microelectronic packages according to the present invention include an integrated circuit mounting substrate, and first and second integrated circuits on the integrated circuit mounting substrate, each of which includes first and second opposing faces and first and second opposing edges, wherein the first faces are adjacent the integrated circuit mounting substrate and the second faces are opposite the integrated circuit mounting substrate. A plurality of solder bumps on the first faces and adjacent the first edges of the first and second integrated circuits extend between the first and second integrated circuits and the integrated circuit mounting substrate. The first and second integrated circuits are oriented on the integrated circuit mounting substrate, such that the second integrated circuit is canted towards the integrated circuit mounting substrate from the first edge to the second edge thereof, and the first face of the second integrated circuit extends on the second face of the second integrated circuit. In first embodiments. the second edge of the second integrated circuit rests on the second face of the first integrated circuit. In other embodiments, the first face of the second integrated circuit rests on the second edge of the first integrated circuit. The integrated circuits may be identical, free of solder reservoir connections and/or mounted at the angles described above.
Microelectronic packaging methods according to embodiments of the present invention orient a second microelectronic substrate at an acute angle relative to a first microelectronic substrate such that a plurality of solder bumps extend between the first and second microelectronic substrates, adjacent an edge of the second microelectronic substrate. The plurality of solder bumps are reflowed to electrically and mechanically connect the second microelectronic substrate to the first microelectronic substrate while confining the plurality of solder bumps to within the edge of the second microelectronic substrate during the reflow. Other embodiments orient a third microelectronic substrate on the first microelectronic substrate to laterally overlap the second microelectronic substrate such that a plurality of second solder bumps electrically and mechanically connect the third microelectronic substrate to the first microelectronic substrate. The plurality of second solder bumps then are reflowed during the reflowing step.
In other method embodiments, the second and third microelectronic substrates are oriented parallel to one another at the acute angle relative to the first microelectronic substrate. In yet other method embodiments, the second microelectronic substrate is oriented such that the edge of the second microelectronic substrate is adjacent the vertex and the third microelectronic substrate is oriented such that a plurality of second solder bumps are adjacent a first edge of the third microelectronic substrate and opposite a second edge of the third microelectronic substrate, the second edge of the third microelectronic substrate is adjacent the vertex and the first edge of the third microelectronic substrate is opposite the vertex. In first embodiments reflowing takes place without increasing the plurality of solder bumps in volume. In other embodiments reflowing may take place while increasing the plurality of solder bumps in volume.